1. Technical Field
This invention relates to the field of optical inspection of semiconductor wafers.
2. Background Art
As manufacturers attempt to tighten ground rules while maintaining device integrity, the elimination of defects in processed semiconductor wafers has become increasingly important. Typically, these defects include discontinuities in the metallization layers as well as particulate contaminants.
Conventionally, in order to eliminate these defects (as well as prevent the shipment of faulty wafers), several of the processed wafers are examined by use of an optical monitoring system. In such optical monitoring systems, a light beam is projected onto the surface of the processed wafer, the wafer reflects the incident light, and the reflected light impinges on a lens system. If defects are present on the wafer, there is a corresponding change in the intensity of the reflected light.
Typically, the reflected light is converted into an electrical signal which is subsequently converted into a visible image on a display screen. By viewing the display screen, an operator can determine the existence of defects on the surface of the semiconductor wafer.
It has been found that the foregoing inspection technique presents several difficulties. First, since reliance is placed upon the operator to detect defects, the inspection takes a relatively long time to complete. If such an inspection were to be carried out on all of the processed wafers, astronomical cost inefficiencies would result. In practice, this detection procedure is carried out on only a small percentage (on the order of 5-10%) of the processed wafers. Such a procedure is grossly inefficient, in that 90-95% of the processed wafers are not tested. Second, in the monitoring system as described above, the resultant electrical signal is representative of the entire surface of the wafer. If this signal were to be digitized and stored for a large number of wafers, the storage required would be quite large.
U.S. Pat. No. 4,376,583 (issued 3/15/83 to Alford et al) discloses an inspection scanning system which does not rely on manual inspection in order to detect defects on the surface of a processed wafer. The inspected wafers are automatically sorted into separate categories according to the nature of the detected defect (if any). Light reflected from the surface of the wafer is compared to various threshold levels to produce a seven-bit address signal. This signal is applied to a flow handling logic network, which is used to construct a digital surface map of the wafer under inspection. The wafer is divided into a plurality of unit areas. Each of these unit areas is assigned a binary flaw code which represents the most severe flaw encountered within the unit area. An algorithm for grading each inspected wafer compares the accumulated number of stored flaw codes to a series of predetermined number and type ranges. The wafers are sorted as a function of where the stored flaws fall within these ranges. The stored flaw codes can also be used to visually display the occurrences of flaws on each inspected wafer as well as to print a map or a histogram of each wafer.
In the inspection scanning system as described above, the occurrence of defects is automatically determined by comparing a derived electrical signal to a series of threshold values. This eliminates the inefficiencies produced by manual inspection of a display screen. However, as in previously-described monitoring systems, the electrical signal produced by the optical inspection system of the Alford patent is representative of the total surface area of the wafer under test. Thus, if the Alford device were used to store representations of the defects on 100% of the processed wafers, the same impractical storage requirements would be presented.
Thus, a need has developed in the semiconductor processing art to provide an automatic defect (or "event") detection system which (a) scans all of the processed wafers in a time efficient manner, and (b) stores representations of the locations of all of the events on 100% of the processed wafers without the use of excessive memory capacity.